During a design process of a processor, dynamic profiling of instructions is traditionally used prior to a hardware design freeze for improving instruction set architecture (ISA) performance and/or improving software performance on a fixed ISA prior to a software design freeze. However, this approach suffers in that the optimal ISA performance is based on simulations that assume certain system behavior (memory accesses for instance) that could be different in reality. As such, optimal ISA performance is based on simulations that may not cover all possibilities that could occur in real life applications post hardware design freeze.